1) Field of the Invention
The present invention relates to a thin-film capacitor, a high-density packaging substrate incorporating the thin-film capacitor, and a method for manufacturing the thin-film capacitor, which enable integral incorporation of electronic devices such as passive components L (inductors and coils), C (condenser or capacitor), and R (resistor), and active components IC (semiconductor) whereby a printed board may be downsized and the degree of density thereof may be intensified, and therefore suitable for realizing a high density packaging substrate which incorporates electronic components.
2) Description of the Related Art
As well known, circuits for multi-layer printed wiring boards have recently been miniaturized and multi-layered, for downsizing and increasing density of the printed boards. In such a multi-layer printed wiring board, requisite components such as active components such as IC, and passive components such as capacitors and resistors are mounted on the surface of the printed wiring board, which are connected, to constitute a desired printed board (multilayer printed wiring board).
Due to recent needs in downsizing and advanced functions for cellular phones, PDA, digital audio-video equipment, or the like, there are increasing demands for downsizing and high integration of printed boards. Thus there is a need for realizing a system-in-package (SiP) in which the aforementioned active components such as IC and the passive components are embedded in a multi-layer printed wiring board, for further increasing the packaging density in the multi-layer printed wiring board.
Today's technical innovation has begun to provide a product (SiP) in which several active components are mounted on one packaging substrate. Researches for embedding active components and passive components into a printed wiring board, i.e., a packaging substrate are also under progress. It is expected that incorporation of a number of electronic components into a multi-layer printed wiring board to provide a high-density packaging substrate will enable further downsizing and increasing in density of the printed boards. Demands for higher density packaging of SiP are thus increasing.
Examples of a passive component to be incorporated include various types of capacitors such as a bypass capacitor and a decoupling capacitor. Incorporation of such capacitors to a packaging substrate will be highly beneficial since capacitors are essential elements, as well as resistors, in an electronic circuit and a number of capacitors are employed in the circuit. A bypass capacitor is employed for eliminating the noise generated at the electric power supply of a digital IC, and thus has to be disposed near the power supply pin of the IC chip. When the bypass capacitor is mounted outside the board, mounting position of the capacitor on the packaging substrate will be limited, which will restrict the freedom of designing a high-density packaging substrate. If the capacitors including such a bypass capacitor are downsized, and specifically made in a form of a thin film to be incorporated into a packaging substrate, the aforementioned problems will be solved, and circuit properties will also be improved. However, a capacitor having a sufficiently thin size available in wiring in the packaging substrate has not yet been obtained so far, and incorporation of the capacitor in the packaging substrate has not thus been achieved.
As a material for a capacitor having a high capacitance, especially for a bypass capacitor, ferroelectric materials are often employed since the ferroelectric material has a high dielectric constant, and dielectric loss thereof does not cause much influences in this case. Generally, a ferroelectric material exhibits a high dielectric loss and may cause problems as to its property for use in high frequency. Therefore, in a frequently employed method, the high-frequency property is improved while dielectric constant is suppressed.
The size of a capacitor will be explained in more detail with an example of the bypass capacitor. Such a capacitor may be produced by laminating a ceramic dielectric substance and a silver-based electrode by screen printing method and sintered (Non-Patent document 1 (IEEE ISAF 2000 (“Proceedings of the 2000 12th IEEE International Symposium on Applications of Ferroelectrics”, Honolulu, Hi., U.S.A., 21, Jul. to 2, Aug., 2000) proceedings, Volume II, pp. 821 to 824.)). Since this capacitor is manufactured by use of such a screen printing method, the thickness of each layer becomes several μm. Therefore, in order to obtain a necessary capacitance, a plurality of layers have to be laminated, which makes the entire thickness in millimeter order.
In order to increase the capacitance of a capacitor, either means for reducing the thickness of a dielectric film, or means for enlarging the surface area of the dielectric film must be taken. However, it is difficult to reduce the thickness of a ceramic dielectric (film) in the screen printing method as described above. Therefore, the dielectric layers have to be laminated for ensuring the surface area.
FIG. 1 is a cross sectional structure of a high-density packaging substrate having desired electronic circuits formed therein; on the supposition that, an IC chip 3 serving as an active component and a resistor 4 and a capacitor 5 serving as passive components can be incorporated between an insulating substrate 1 and an interlayer insulating layer 2 of the high-density packaging substrate by setting the electronic components in the wirings. The conventional multi-layer ceramic capacitor can not be employed as the capacitor 5 in such a structure, since the conventional ceramic capacitor has a millimeter order of thickness whereas each of other components has thickness several tens of micrometers, and the conventional capacitor can not be embedded into such a thin multi-layer structure of the packaging substrate. If the conventional capacitor is forcedly embedded, a part of the packaging substrate below the capacitor has to be concaved, and the via has to be vertically extended to expand the gap between an upper wiring layer and a lower wiring layer, which would inhibit thinning of the packaging substrate and result in a unsatisfactory product in terms of technology and cost. Particularly, great restrictions will be imposed on a bypass capacitor which has to be disposed near the power supply pin of an IC chip.